// Copyright (C) 2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License // Subscription Agreement, the Intel Quartus Prime License Agreement, // the Intel FPGA IP License Agreement, or other applicable license // agreement, including, without limitation, that your use is for // the sole purpose of programming logic devices manufactured by // Intel and sold by Intel or its authorized distributors. Please // refer to the applicable agreement for further details. // VENDOR "Altera" // PROGRAM "Quartus Prime" // VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" // DATE "04/28/2019 11:46:04" // // Device: Altera 5CSXFC6D6F31C6 Package FBGA896 // // // This Verilog file should be used for ModelSim-Altera (Verilog) only // `timescale 1 ps/ 1 ps module sregister ( clk, choose, en, data_in, inone, Q); input clk; input [2:0] choose; input en; input [7:0] data_in; input inone; output [7:0] Q; // Design Ports Information // Q[0] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default // Q[1] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default // Q[2] => Location: PIN_AC23, I/O Standard: 2.5 V, Current Strength: Default // Q[3] => Location: PIN_AD24, I/O Standard: 2.5 V, Current Strength: Default // Q[4] => Location: PIN_AG25, I/O Standard: 2.5 V, Current Strength: Default // Q[5] => Location: PIN_AF25, I/O Standard: 2.5 V, Current Strength: Default // Q[6] => Location: PIN_AE24, I/O Standard: 2.5 V, Current Strength: Default // Q[7] => Location: PIN_AF24, I/O Standard: 2.5 V, Current Strength: Default // choose[2] => Location: PIN_AA15, I/O Standard: 2.5 V, Current Strength: Default // en => Location: PIN_AA30, I/O Standard: 2.5 V, Current Strength: Default // choose[1] => Location: PIN_AA14, I/O Standard: 2.5 V, Current Strength: Default // choose[0] => Location: PIN_AK4, I/O Standard: 2.5 V, Current Strength: Default // data_in[0] => Location: PIN_AB30, I/O Standard: 2.5 V, Current Strength: Default // clk => Location: PIN_AJ4, I/O Standard: 2.5 V, Current Strength: Default // data_in[1] => Location: PIN_Y27, I/O Standard: 2.5 V, Current Strength: Default // data_in[2] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default // data_in[3] => Location: PIN_AC30, I/O Standard: 2.5 V, Current Strength: Default // data_in[4] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default // data_in[5] => Location: PIN_V25, I/O Standard: 2.5 V, Current Strength: Default // data_in[6] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default // inone => Location: PIN_AC29, I/O Standard: 2.5 V, Current Strength: Default // data_in[7] => Location: PIN_AD30, I/O Standard: 2.5 V, Current Strength: Default wire gnd; wire vcc; wire unknown; assign gnd = 1'b0; assign vcc = 1'b1; assign unknown = 1'bx; tri1 devclrn; tri1 devpor; tri1 devoe; wire \~QUARTUS_CREATED_GND~I_combout ; wire \clk~input_o ; wire \clk~inputCLKENA0_outclk ; wire \choose[0]~input_o ; wire \choose[2]~input_o ; wire \choose[1]~input_o ; wire \en~input_o ; wire \Q[0]~1_combout ; wire \data_in[0]~input_o ; wire \Q[0]~0_combout ; wire \data_in[7]~input_o ; wire \inone~input_o ; wire \Mux0~0_combout ; wire \data_in[6]~input_o ; wire \data_in[5]~input_o ; wire \data_in[4]~input_o ; wire \data_in[3]~input_o ; wire \data_in[2]~input_o ; wire \data_in[1]~input_o ; wire \Q~3_combout ; wire \Q[1]~reg0_q ; wire \Q~4_combout ; wire \Q[2]~reg0_q ; wire \Q~5_combout ; wire \Q[3]~reg0_q ; wire \Q~6_combout ; wire \Q[4]~reg0_q ; wire \Q~7_combout ; wire \Q[5]~reg0_q ; wire \Q~12_combout ; wire \Q[6]~reg0_q ; wire \Q~8_combout ; wire \Q[7]~reg0_q ; wire \Q~2_combout ; wire \Q[0]~reg0_q ; // Location: IOOBUF_X89_Y11_N45 cyclonev_io_obuf \Q[0]~output ( .i(\Q[0]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[0]), .obar()); // synopsys translate_off defparam \Q[0]~output .bus_hold = "false"; defparam \Q[0]~output .open_drain_output = "false"; defparam \Q[0]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X89_Y9_N22 cyclonev_io_obuf \Q[1]~output ( .i(\Q[1]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[1]), .obar()); // synopsys translate_off defparam \Q[1]~output .bus_hold = "false"; defparam \Q[1]~output .open_drain_output = "false"; defparam \Q[1]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X86_Y0_N19 cyclonev_io_obuf \Q[2]~output ( .i(\Q[2]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[2]), .obar()); // synopsys translate_off defparam \Q[2]~output .bus_hold = "false"; defparam \Q[2]~output .open_drain_output = "false"; defparam \Q[2]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X88_Y0_N37 cyclonev_io_obuf \Q[3]~output ( .i(\Q[3]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[3]), .obar()); // synopsys translate_off defparam \Q[3]~output .bus_hold = "false"; defparam \Q[3]~output .open_drain_output = "false"; defparam \Q[3]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X78_Y0_N36 cyclonev_io_obuf \Q[4]~output ( .i(\Q[4]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[4]), .obar()); // synopsys translate_off defparam \Q[4]~output .bus_hold = "false"; defparam \Q[4]~output .open_drain_output = "false"; defparam \Q[4]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X86_Y0_N36 cyclonev_io_obuf \Q[5]~output ( .i(\Q[5]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[5]), .obar()); // synopsys translate_off defparam \Q[5]~output .bus_hold = "false"; defparam \Q[5]~output .open_drain_output = "false"; defparam \Q[5]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X88_Y0_N54 cyclonev_io_obuf \Q[6]~output ( .i(\Q[6]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[6]), .obar()); // synopsys translate_off defparam \Q[6]~output .bus_hold = "false"; defparam \Q[6]~output .open_drain_output = "false"; defparam \Q[6]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOOBUF_X74_Y0_N59 cyclonev_io_obuf \Q[7]~output ( .i(\Q[7]~reg0_q ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), .parallelterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(Q[7]), .obar()); // synopsys translate_off defparam \Q[7]~output .bus_hold = "false"; defparam \Q[7]~output .open_drain_output = "false"; defparam \Q[7]~output .shift_series_termination_control = "false"; // synopsys translate_on // Location: IOIBUF_X22_Y0_N35 cyclonev_io_ibuf \clk~input ( .i(clk), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\clk~input_o )); // synopsys translate_off defparam \clk~input .bus_hold = "false"; defparam \clk~input .simulate_z_as = "z"; // synopsys translate_on // Location: CLKCTRL_G6 cyclonev_clkena \clk~inputCLKENA0 ( .inclk(\clk~input_o ), .ena(vcc), .outclk(\clk~inputCLKENA0_outclk ), .enaout()); // synopsys translate_off defparam \clk~inputCLKENA0 .clock_type = "global clock"; defparam \clk~inputCLKENA0 .disable_mode = "low"; defparam \clk~inputCLKENA0 .ena_register_mode = "always enabled"; defparam \clk~inputCLKENA0 .ena_register_power_up = "high"; defparam \clk~inputCLKENA0 .test_syn = "high"; // synopsys translate_on // Location: IOIBUF_X22_Y0_N52 cyclonev_io_ibuf \choose[0]~input ( .i(choose[0]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\choose[0]~input_o )); // synopsys translate_off defparam \choose[0]~input .bus_hold = "false"; defparam \choose[0]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X36_Y0_N18 cyclonev_io_ibuf \choose[2]~input ( .i(choose[2]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\choose[2]~input_o )); // synopsys translate_off defparam \choose[2]~input .bus_hold = "false"; defparam \choose[2]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X36_Y0_N1 cyclonev_io_ibuf \choose[1]~input ( .i(choose[1]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\choose[1]~input_o )); // synopsys translate_off defparam \choose[1]~input .bus_hold = "false"; defparam \choose[1]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y21_N21 cyclonev_io_ibuf \en~input ( .i(en), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\en~input_o )); // synopsys translate_off defparam \en~input .bus_hold = "false"; defparam \en~input .simulate_z_as = "z"; // synopsys translate_on // Location: LABCELL_X88_Y12_N18 cyclonev_lcell_comb \Q[0]~1 ( // Equation(s): // \Q[0]~1_combout = ( \choose[1]~input_o & ( \en~input_o & ( !\choose[0]~input_o ) ) ) # ( !\choose[1]~input_o & ( \en~input_o & ( (\choose[2]~input_o ) # (\choose[0]~input_o ) ) ) ) .dataa(gnd), .datab(!\choose[0]~input_o ), .datac(!\choose[2]~input_o ), .datad(gnd), .datae(!\choose[1]~input_o ), .dataf(!\en~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q[0]~1_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q[0]~1 .extended_lut = "off"; defparam \Q[0]~1 .lut_mask = 64'h000000003F3FCCCC; defparam \Q[0]~1 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X89_Y21_N4 cyclonev_io_ibuf \data_in[0]~input ( .i(data_in[0]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[0]~input_o )); // synopsys translate_off defparam \data_in[0]~input .bus_hold = "false"; defparam \data_in[0]~input .simulate_z_as = "z"; // synopsys translate_on // Location: LABCELL_X88_Y12_N51 cyclonev_lcell_comb \Q[0]~0 ( // Equation(s): // \Q[0]~0_combout = ( \en~input_o & ( (\choose[1]~input_o ) # (\choose[2]~input_o ) ) ) .dataa(gnd), .datab(gnd), .datac(!\choose[2]~input_o ), .datad(!\choose[1]~input_o ), .datae(gnd), .dataf(!\en~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q[0]~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q[0]~0 .extended_lut = "off"; defparam \Q[0]~0 .lut_mask = 64'h000000000FFF0FFF; defparam \Q[0]~0 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X89_Y25_N38 cyclonev_io_ibuf \data_in[7]~input ( .i(data_in[7]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[7]~input_o )); // synopsys translate_off defparam \data_in[7]~input .bus_hold = "false"; defparam \data_in[7]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y20_N95 cyclonev_io_ibuf \inone~input ( .i(inone), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\inone~input_o )); // synopsys translate_off defparam \inone~input .bus_hold = "false"; defparam \inone~input .simulate_z_as = "z"; // synopsys translate_on // Location: LABCELL_X88_Y12_N12 cyclonev_lcell_comb \Mux0~0 ( // Equation(s): // \Mux0~0_combout = ( \inone~input_o & ( ((\choose[0]~input_o & \data_in[7]~input_o )) # (\choose[2]~input_o ) ) ) # ( !\inone~input_o & ( (!\choose[0]~input_o & (\choose[2]~input_o )) # (\choose[0]~input_o & (!\choose[2]~input_o & // \data_in[7]~input_o )) ) ) .dataa(gnd), .datab(!\choose[0]~input_o ), .datac(!\choose[2]~input_o ), .datad(!\data_in[7]~input_o ), .datae(!\inone~input_o ), .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Mux0~0_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Mux0~0 .extended_lut = "off"; defparam \Mux0~0 .lut_mask = 64'h0C3C0F3F0C3C0F3F; defparam \Mux0~0 .shared_arith = "off"; // synopsys translate_on // Location: IOIBUF_X89_Y20_N78 cyclonev_io_ibuf \data_in[6]~input ( .i(data_in[6]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[6]~input_o )); // synopsys translate_off defparam \data_in[6]~input .bus_hold = "false"; defparam \data_in[6]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y20_N61 cyclonev_io_ibuf \data_in[5]~input ( .i(data_in[5]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[5]~input_o )); // synopsys translate_off defparam \data_in[5]~input .bus_hold = "false"; defparam \data_in[5]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y20_N44 cyclonev_io_ibuf \data_in[4]~input ( .i(data_in[4]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[4]~input_o )); // synopsys translate_off defparam \data_in[4]~input .bus_hold = "false"; defparam \data_in[4]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y25_N55 cyclonev_io_ibuf \data_in[3]~input ( .i(data_in[3]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[3]~input_o )); // synopsys translate_off defparam \data_in[3]~input .bus_hold = "false"; defparam \data_in[3]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y21_N38 cyclonev_io_ibuf \data_in[2]~input ( .i(data_in[2]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[2]~input_o )); // synopsys translate_off defparam \data_in[2]~input .bus_hold = "false"; defparam \data_in[2]~input .simulate_z_as = "z"; // synopsys translate_on // Location: IOIBUF_X89_Y25_N21 cyclonev_io_ibuf \data_in[1]~input ( .i(data_in[1]), .ibar(gnd), .dynamicterminationcontrol(gnd), .o(\data_in[1]~input_o )); // synopsys translate_off defparam \data_in[1]~input .bus_hold = "false"; defparam \data_in[1]~input .simulate_z_as = "z"; // synopsys translate_on // Location: LABCELL_X88_Y12_N30 cyclonev_lcell_comb \Q~3 ( // Equation(s): // \Q~3_combout = ( \Q[0]~reg0_q & ( (!\Q[0]~0_combout & (\Q[0]~1_combout & (\data_in[1]~input_o ))) # (\Q[0]~0_combout & ((!\Q[0]~1_combout ) # ((\Q[2]~reg0_q )))) ) ) # ( !\Q[0]~reg0_q & ( (\Q[0]~1_combout & ((!\Q[0]~0_combout & // (\data_in[1]~input_o )) # (\Q[0]~0_combout & ((\Q[2]~reg0_q ))))) ) ) .dataa(!\Q[0]~0_combout ), .datab(!\Q[0]~1_combout ), .datac(!\data_in[1]~input_o ), .datad(!\Q[2]~reg0_q ), .datae(gnd), .dataf(!\Q[0]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~3_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~3 .extended_lut = "off"; defparam \Q~3 .lut_mask = 64'h0213021346574657; defparam \Q~3 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N32 dffeas \Q[1]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~3_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[1]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[1]~reg0 .is_wysiwyg = "true"; defparam \Q[1]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N0 cyclonev_lcell_comb \Q~4 ( // Equation(s): // \Q~4_combout = ( \Q[3]~reg0_q & ( \Q[1]~reg0_q & ( ((\Q[0]~1_combout & \data_in[2]~input_o )) # (\Q[0]~0_combout ) ) ) ) # ( !\Q[3]~reg0_q & ( \Q[1]~reg0_q & ( (!\Q[0]~1_combout & ((\Q[0]~0_combout ))) # (\Q[0]~1_combout & (\data_in[2]~input_o & // !\Q[0]~0_combout )) ) ) ) # ( \Q[3]~reg0_q & ( !\Q[1]~reg0_q & ( (\Q[0]~1_combout & ((\Q[0]~0_combout ) # (\data_in[2]~input_o ))) ) ) ) # ( !\Q[3]~reg0_q & ( !\Q[1]~reg0_q & ( (\Q[0]~1_combout & (\data_in[2]~input_o & !\Q[0]~0_combout )) ) ) ) .dataa(!\Q[0]~1_combout ), .datab(!\data_in[2]~input_o ), .datac(!\Q[0]~0_combout ), .datad(gnd), .datae(!\Q[3]~reg0_q ), .dataf(!\Q[1]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~4_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~4 .extended_lut = "off"; defparam \Q~4 .lut_mask = 64'h101015151A1A1F1F; defparam \Q~4 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N2 dffeas \Q[2]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~4_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[2]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[2]~reg0 .is_wysiwyg = "true"; defparam \Q[2]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N57 cyclonev_lcell_comb \Q~5 ( // Equation(s): // \Q~5_combout = ( \Q[2]~reg0_q & ( \Q[4]~reg0_q & ( ((\data_in[3]~input_o & \Q[0]~1_combout )) # (\Q[0]~0_combout ) ) ) ) # ( !\Q[2]~reg0_q & ( \Q[4]~reg0_q & ( (\Q[0]~1_combout & ((\Q[0]~0_combout ) # (\data_in[3]~input_o ))) ) ) ) # ( \Q[2]~reg0_q // & ( !\Q[4]~reg0_q & ( (!\Q[0]~1_combout & ((\Q[0]~0_combout ))) # (\Q[0]~1_combout & (\data_in[3]~input_o & !\Q[0]~0_combout )) ) ) ) # ( !\Q[2]~reg0_q & ( !\Q[4]~reg0_q & ( (\data_in[3]~input_o & (\Q[0]~1_combout & !\Q[0]~0_combout )) ) ) ) .dataa(!\data_in[3]~input_o ), .datab(gnd), .datac(!\Q[0]~1_combout ), .datad(!\Q[0]~0_combout ), .datae(!\Q[2]~reg0_q ), .dataf(!\Q[4]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~5_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~5 .extended_lut = "off"; defparam \Q~5 .lut_mask = 64'h050005F0050F05FF; defparam \Q~5 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N59 dffeas \Q[3]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~5_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[3]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[3]~reg0 .is_wysiwyg = "true"; defparam \Q[3]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N48 cyclonev_lcell_comb \Q~6 ( // Equation(s): // \Q~6_combout = ( \Q[3]~reg0_q & ( (!\Q[0]~0_combout & (\data_in[4]~input_o & ((\Q[0]~1_combout )))) # (\Q[0]~0_combout & (((!\Q[0]~1_combout ) # (\Q[5]~reg0_q )))) ) ) # ( !\Q[3]~reg0_q & ( (\Q[0]~1_combout & ((!\Q[0]~0_combout & // (\data_in[4]~input_o )) # (\Q[0]~0_combout & ((\Q[5]~reg0_q ))))) ) ) .dataa(!\Q[0]~0_combout ), .datab(!\data_in[4]~input_o ), .datac(!\Q[5]~reg0_q ), .datad(!\Q[0]~1_combout ), .datae(gnd), .dataf(!\Q[3]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~6_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~6 .extended_lut = "off"; defparam \Q~6 .lut_mask = 64'h0027002755275527; defparam \Q~6 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N50 dffeas \Q[4]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~6_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[4]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[4]~reg0 .is_wysiwyg = "true"; defparam \Q[4]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N33 cyclonev_lcell_comb \Q~7 ( // Equation(s): // \Q~7_combout = ( \Q[4]~reg0_q & ( (!\Q[0]~0_combout & (\Q[0]~1_combout & ((\data_in[5]~input_o )))) # (\Q[0]~0_combout & ((!\Q[0]~1_combout ) # ((\Q[6]~reg0_q )))) ) ) # ( !\Q[4]~reg0_q & ( (\Q[0]~1_combout & ((!\Q[0]~0_combout & // ((\data_in[5]~input_o ))) # (\Q[0]~0_combout & (\Q[6]~reg0_q )))) ) ) .dataa(!\Q[0]~0_combout ), .datab(!\Q[0]~1_combout ), .datac(!\Q[6]~reg0_q ), .datad(!\data_in[5]~input_o ), .datae(gnd), .dataf(!\Q[4]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~7_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~7 .extended_lut = "off"; defparam \Q~7 .lut_mask = 64'h0123012345674567; defparam \Q~7 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N35 dffeas \Q[5]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~7_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[5]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[5]~reg0 .is_wysiwyg = "true"; defparam \Q[5]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N42 cyclonev_lcell_comb \Q~12 ( // Equation(s): // \Q~12_combout = ( !\choose[1]~input_o & ( (\en~input_o & ((!\choose[2]~input_o & (\data_in[6]~input_o & (\choose[0]~input_o ))) # (\choose[2]~input_o & (((\Q[7]~reg0_q )))))) ) ) # ( \choose[1]~input_o & ( (\en~input_o & (((!\choose[0]~input_o & // ((\Q[7]~reg0_q ))) # (\choose[0]~input_o & (\Q[5]~reg0_q ))))) ) ) .dataa(!\en~input_o ), .datab(!\data_in[6]~input_o ), .datac(!\Q[5]~reg0_q ), .datad(!\choose[0]~input_o ), .datae(!\choose[1]~input_o ), .dataf(!\Q[7]~reg0_q ), .datag(!\choose[2]~input_o ), .cin(gnd), .sharein(gnd), .combout(\Q~12_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~12 .extended_lut = "on"; defparam \Q~12 .lut_mask = 64'h0010000505155505; defparam \Q~12 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N44 dffeas \Q[6]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~12_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[6]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[6]~reg0 .is_wysiwyg = "true"; defparam \Q[6]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N36 cyclonev_lcell_comb \Q~8 ( // Equation(s): // \Q~8_combout = ( !\choose[1]~input_o & ( (\en~input_o & (\Mux0~0_combout & (((\choose[0]~input_o )) # (\Q[7]~reg0_q )))) ) ) # ( \choose[1]~input_o & ( (\en~input_o & ((!\choose[0]~input_o & (\Mux0~0_combout & (\Q[0]~reg0_q ))) # // (\choose[0]~input_o & (((\Q[6]~reg0_q )))))) ) ) .dataa(!\en~input_o ), .datab(!\Mux0~0_combout ), .datac(!\Q[0]~reg0_q ), .datad(!\choose[0]~input_o ), .datae(!\choose[1]~input_o ), .dataf(!\Q[6]~reg0_q ), .datag(!\Q[7]~reg0_q ), .cin(gnd), .sharein(gnd), .combout(\Q~8_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~8 .extended_lut = "on"; defparam \Q~8 .lut_mask = 64'h0111010001110155; defparam \Q~8 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N38 dffeas \Q[7]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~8_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[7]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[7]~reg0 .is_wysiwyg = "true"; defparam \Q[7]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X88_Y12_N24 cyclonev_lcell_comb \Q~2 ( // Equation(s): // \Q~2_combout = ( \Q[7]~reg0_q & ( \Q[1]~reg0_q & ( (!\Q[0]~1_combout & (((\Q[0]~0_combout & \choose[2]~input_o )))) # (\Q[0]~1_combout & (((\Q[0]~0_combout )) # (\data_in[0]~input_o ))) ) ) ) # ( !\Q[7]~reg0_q & ( \Q[1]~reg0_q & ( (\Q[0]~1_combout // & ((\Q[0]~0_combout ) # (\data_in[0]~input_o ))) ) ) ) # ( \Q[7]~reg0_q & ( !\Q[1]~reg0_q & ( (!\Q[0]~1_combout & (((\Q[0]~0_combout & \choose[2]~input_o )))) # (\Q[0]~1_combout & (\data_in[0]~input_o & (!\Q[0]~0_combout ))) ) ) ) # ( !\Q[7]~reg0_q // & ( !\Q[1]~reg0_q & ( (\Q[0]~1_combout & (\data_in[0]~input_o & !\Q[0]~0_combout )) ) ) ) .dataa(!\Q[0]~1_combout ), .datab(!\data_in[0]~input_o ), .datac(!\Q[0]~0_combout ), .datad(!\choose[2]~input_o ), .datae(!\Q[7]~reg0_q ), .dataf(!\Q[1]~reg0_q ), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\Q~2_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \Q~2 .extended_lut = "off"; defparam \Q~2 .lut_mask = 64'h1010101A1515151F; defparam \Q~2 .shared_arith = "off"; // synopsys translate_on // Location: FF_X88_Y12_N26 dffeas \Q[0]~reg0 ( .clk(\clk~inputCLKENA0_outclk ), .d(\Q~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), .ena(vcc), .devclrn(devclrn), .devpor(devpor), .q(\Q[0]~reg0_q ), .prn(vcc)); // synopsys translate_off defparam \Q[0]~reg0 .is_wysiwyg = "true"; defparam \Q[0]~reg0 .power_up = "low"; // synopsys translate_on // Location: LABCELL_X17_Y30_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): .dataa(gnd), .datab(gnd), .datac(gnd), .datad(gnd), .datae(gnd), .dataf(gnd), .datag(gnd), .cin(gnd), .sharein(gnd), .combout(\~QUARTUS_CREATED_GND~I_combout ), .sumout(), .cout(), .shareout()); // synopsys translate_off defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off"; defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000; defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off"; // synopsys translate_on endmodule